A 17-level octuple boost switched-capacitor inverter with lower voltage stress on devices

This paper presents a new structure for switched-capacitor multilevel inverter with octuple voltage gain capability. The proposed inverter utilizes three capacitors, 13 semiconductor switches, three diodes, and an input voltage source to achieve a 17-level output voltage. The switched capacitors naturally achieve voltage balancing without the need for sensors or additional circuits, indicating the ease of control of the proposed structure. To control the inrush current of the switched capacitors, a charge limiting inductor has been utilized in the charging path of the capacitors. This not only reduces the inrush current of the capacitors and the input source current but also enables faster capacitor charging and extends their lifetime. The switches used in the proposed structure can withstand a maximum of 4 times the input voltage value or the half of the maximum output voltage, which is a significant advantage for the proposed structure. A detailed comparison with similar structures is provided to examine the advantages and disadvantages of the suggested inverter. The procedure of self-voltage balancing of the capacitors and the functional modes of the proposed topology has been explained in detail. The proposed structure is suitable for applications such as renewable energy sources transfer to load or grid. The performance of the proposed topology under different conditions is confirmed through simulation in the Matlab\Simulink software and the implementation of the laboratory sample.

• Use of a single input voltage source • Octuple boost factor • Generation of positive and negative voltage levels without the need for an H-bridge module • Lower voltage stress of switches, lower losses and lower cost • Self-balancing capability for voltage of capacitors • Capability to perform in inductive loads • Reducing inrush currents in capacitors using a charge current limiting inductor In the following, the structure of the paper is explained as follows: The proposed structure is introduced in section two, then the principles of operation, switching modes, and charging and discharging of capacitors are described in detail.In the following, the method of calculating and designing the utilized capacitors in the proposed structure is illustrated.In the third section, the losses of the proposed converter have been evaluated and, a comparative evaluation has been carried out in section four.The results of the simulation and implementation of the laboratory setup are presented in the fifth section.In the sixth section, conclusions and summaries are made.

Proposed structure
The proposed 17-level inverter circuit is displayed in Fig. 1.According to this figure, the proposed structure consists of a DC power supply (V in ), 13 switches, 3 diodes, and 3 capacitors.The rated voltage of capacitors C 1 , C 2 , and C 3 are V in , 2V in , and 4V in , respectively.An inductor paralleled with a diode in series with the input voltage source has been utilized to control the inrush charging current of the capacitors.In addition to controlling the charging current of the capacitor, this also alleviates the input current peak.The proposed structure does www.nature.com/scientificreports/not need an H-bridge module to generate bipolar voltage levels, and none of the power switches withstand the maximum output voltage.Figure 2 demonstrates the paths of current passing and how capacitors are charged and discharged to generate different voltage levels.Table 1 reveals the power switches that produce each voltage level.In this Table, the on and off states for the switches are indicated by 1 and 0, respectively.Besides, C means charging, D means discharging, and-means no change in capacitor voltage.
According to Fig. 2, it is clear that to generate different voltage levels, 6 power electronic switches are placed in the path of the load current.Meanwhile, in most levels, another power switch is turned on to charge the capacitors as well.In most 17-level structures, the number of conducting power switches in the path of the load current or capacitor charging is more than this number.This point will decrease the conduction losses of the proposed structure, which will be studied in the relevant section.

Capacitor calculations
In switched-capacitor multi-level inverters, self balancing of the capacitors' voltage is provided by their charging and discharging using parallel and series connection with the input DC voltage source, respectively.Choosing the suitable capacitor capacity has a significant influence on reducing capacitor voltage ripple and depends on various factors such as the longest discharging time (LDT) and loading conditions 18 .By reducing the voltage ripple of the capacitor, the losses of the converter are decreased, and the quality of the output voltage waveform is enhanced.Figure 3 displays how capacitors are discharged to create different output voltage levels.The capacitor C 1 , which is fixed at the voltage of V in , is discharged at the voltage levels of 2V in , 4V in , 6V in , and 8V in , and charged www.nature.com/scientificreports/ at the voltage levels of V in , 3V in , 5V in , and 7V in .The capacitor C 2 , which is fixed at the voltage of 2V in , is charged at the voltage levels of 2V in , and 6V in , and charged at the voltage levels of 3V in , 4V in , 7V in , and 8V in .Besides, the capacitor C 3 , which is fixed at the voltage of 4V in , is discharged at 5V in to 8V in , and charged at the voltage level of 4V in .Considering the longest discharging intervals, the capacity of C 1 , and C 2 will be suitable values, and only the capacity of C 3 is the main challenge of the proposed structure.
The discharge amount of capacitors is calculated by Eq. ( 1), in which I P is the peak value of the output current, t a and t b are the initial and final moments of the corresponding capacitor discharge, and f o is the output frequency.
According to Eq. (1) and the longest discharging time of capacitors in Fig. 3, it is possible to calculate the discharge value of capacitors C 1 to C 3 for a pure resistive load, which is the worst loading condition through Eqs.(2) to (4).
(1)  In Fig. 3, the output voltage generation pattern based on the fundamental frequency switching technique is illustrated, which can divide the half-cycle period (T/2) into 16 time steps.These time steps are calculated by Eq. ( 5).
If the allowable voltage ripple of capacitors (V R ) is considered between 5 and 10%, the capacity of the capacitors can be calculated by the following equation.

Inverter losses evaluation
In general, losses of switched-capacitor multi-level inverters are divided into three parts, which are studied in this section.The switched-capacitor multi-level inverter power loss is according to Eq. ( 7), where P S is the switching loss, P C is the conduction loss, and P Ripple is the ripple loss.The switching and conduction losses are related to power semiconductor equipment, and the ripple losses are related to voltage drop and voltage ripple of capacitors 19,20 .

Switching losses
Switching losses occur due to delays in the conduction behavior of the switches.Since the switches dissipate energy both during the on-state and off-state, the energy loss of a semiconductor switch can be calculated using Eq. ( 8).In this equation, N ON and E ON represent the number of times the switch turns on and the energy dissipated during the on-state, respectively.While N OFF and E OFF represent the number of times the switch turns off and the energy dissipated during the off-state, respectively.

Conduction losses
The internal resistance of the semiconductor devices that are in the path of current constitutes the conduction losses.The equivalent circuit of conduction losses for the proposed structure is shown in Fig. 4 based on the output voltage levels.By applying KVL (Kirchhoff 's Voltage Law) in these circuits, the conduction losses for each output voltage level can be calculated using the equations provided.It should be noted that, the charge current is calculated using the equations provided in Table 2.
Over a complete cycle, the instantaneous conduction losses are averaged, and the average conduction losses for each output voltage level are presented in Table 3.By calculating the average conduction losses separately for each level, the total conduction losses can be calculated using the following equation: (5) Equivalent circuit of conduction losses of the proposed structure.

Output voltage
Charging current (i C ) Average conduction losses at each voltage level.

Ripple loss
The energy lost when the capacitor is charged through the source is called ripple loss, which is affected by load characteristics and switching frequency.The ripple losses can be calculated using Eq.(18).In this equation, capacitor voltage ripple ΔV C is calculated through Eqs.(19) to (21).
Using the provided equations, the losses of the proposed inverter can be calculated according to Fig. 5.The calculations are performed under the conditions where the input voltage is 100 V, the output voltage is 800 V, the output current is 2.8 amperes, a resistive-inductive load with an impedance of 250 ohms, 80 mH, and the output power is 1173 watts.The loss calculations were performed using the information provided in the datasheets for the IGBT switch IKFW60N60DH3E (600V/50A) and the diode FFPF30U60S (600V/30A).The energy loss curves (E OFF , E ON ) relative to the collector-emitter voltage of the switch are provided by the manufacturer, and these curves are used in simulating losses.

Comparative evaluation
To more accurately examine the advantages and disadvantages of the proposed structure, a comprehensive comparison with other 17-level switched-capacitor structures in terms of the number of voltage sources (N dc ), the number of power switches (N S ), the number of drivers (N dr ), the number of capacitors (N C ), the number of diodes (N D ), the maximum number of on power switches in the load path (N ms ), the maximum standing voltage (MSV) of the power switches, the total standing voltage (TSV) of all the power switches, the boost factor (BF), and the cost factor (CF) are provided in Table 4.In this table, the cost factor is presented based on the ratio of the number of devices per the output levels and is calculated by Eq. ( 22) 21 .In this equation, α is a weighting factor that can be considered 0.5 or 1.5 5 .The weighting factor is multiplied by TSV to calculate the cost factor under fair conditions.If the priority of design and comparison is with the number of circuit elements, this parameter is considered 0.5, and if the priority of design and comparison is with blocking voltage of equipment, this parameter is considered 1.5.Common CHB, NPC, and FC structures require many components to generate 17 voltage levels.This issue has caused them to have a high cost factor and are not cost-effective for various applications.The structures presented in 22,23,25 , and 27 are not single-source and produce 17-level voltage in the case of asymmetric sources.The main challenge of these structures is how to provide DC voltage sources.According to Table 4, the TSV of the proposed structure is lower than compared to single-source 17-level structures.Additionally, the structures presented in 25,27 , and 28 need switches with a high-rated voltage because the maximum voltage that can (18) www.nature.com/scientificreports/be tolerated by some switches in these structures is eight times the input voltage, and this issue can limit their application.At the same time, the MSV of the propsosed structure is half of the maximum output voltage.This feature improves the application of the proposed structure with lower reated voltage swtches, which will naturally require less cost.According to Table 4, the proposed 17-level switched capacitor structure introduces lower cost factor in comparison wth other similar recent presented 17-level structures for both 0.5 and 1.5 weighting factors.Also, the maximum number of conductiong power switches in the load path is suitable count compared to other similar 17-level structures.Figure 6 illustrates the efficiency comparison of the proposed structure with other structures for different output powers.The switching pattern is effective in the efficiency of the converters.The structures controlled by low-frequency pattrens such as Nearest Level Control (NLC) or Selective Harmonic Elimination (SHE) strategy have fewer losses, and as a result, show higher efficiency.In this comparison, the efficiency of all structures has been evaluated based on the NLC modulation scheme to achieve a fair and just comparison.One of the critical parameters in the total losses of the multilevel inverters is the number of switches in ON mode at different voltage levels.The lower the number of ON switches in the load and capacitor charging paths, the lower the conduction losses, and as a result, the total losses of the inverter are decreased.Based on the comparison Table, multi-source structures have fewer ON switches in producing voltage levels due to the utilization of more DC sources.In the proposed structure, a maximum of six switches are placed in the path of the output load current, which is the lowest value for single-source structures.Therefore, the conduction losses of the proposed structure can be lower than those of similar structures based on the number of conducting switches in different voltage levels.Following Fig. 6, the efficiency of the structures decreases to some extent with the increase of the output power.The structure of 15 is more efficient than the proposed structure at low powers with a tiny difference.However, by increasing the output power, the efficiency of the proposed structure is more than the efficiency of the structure in 15 .According to this figure, the efficiency of the proposed structure is equal to or better than

Simulation and laboratory results
In this section, simulation and experimental results have been presented to check the correctness of the proposed circuit's performance, as well as the analyses illustrated in the previous sections.Nearest Level Control (NLC) switching scheme has been used to control the power switches of the proposed structure.In this method, the nearest voltage level traces the sinusoidal voltage waveform, and thus, voltage levels are created.Figure 7 displays the implemented switching scheme.The results of simulation and implementation are demonstrated under various conditions including pure resistive as well as resistive-inductive loads, dynamic change in load, modulation index, and output frequency.Moreover, the input voltage and current waveform, the voltage waveform of the switches to show their voltage stress, and the voltage and current waveform of the capacitors to check the voltage and current stress of the capacitors and the switches on the capacitors charging path are displayed as well.
The parameters used for simulating and implementing the proposed structure are given in Table 5.The circuit diagram of the proposed structure implemented in the laboratory environment is shown in Fig. 8.The proposed inverter prototype was tested and evaluated with an output power of 175 W for a resistive-inductive load and an output power of 245 W for a purely resistive load.Figure 9 displays the output voltage and current under resistive-inductive load (Z l = 80 Ω + 120 mH). Figure 9a shows the results of the simulation, according to which the output voltage is stepped and pseudo-sinusoidal and has 17 voltage levels.The peak output voltage is 175 V, and the peak output current is about 2 A. According to this figure, the capability to increase the output voltage by 8 times is confirmed compared to the input voltage of 23 V. Due to the low voltage ripple of the capacitors, the steps of different voltage levels are equal to 23 V. Figure 9b is related to the results of implementing the output voltage and current in similar conditions.In Fig. 9c the harmonic distortion of the output voltage is shown that the THD of the 17-level output voltage is 4.98%.To evaluate the performance of the inverter in dynamic conditions, load dynamic change has been assessed in Fig. 11.In this figure, the performance of the proposed structure is shown for the sudden change in output load at t = 0.305 s from the pure resistive load of Z l = 90 Ω to the resistive-conductive load of Z l = 80 Ω + 120 mH.According to this figure, the 17-level waveform of the output voltage does not change under the sudden load change condition.The proposed inverter can adequately feed different loads with different power factors, and under load changes as well.
Figure 12 presents the output voltage and current under sudden change of modulation index.According to this figure, by changing the modulation index from 1 to 0.7 at t = 0.3 s, the output voltage waveform reaches from 17 to 13 levels.In addition, the output voltage and current will change from 175 to 130 V and from 2.4 A to 2 A, respectively.In this case, when the modulation index is changed from 0.7 to 0.5, the 13-level output voltage with a peak of 130 V changes to a 9-level voltage with a peak of 90 V.It is apparent that the proposed structure can correctly create output levels in both cases of dynamic change in modulation index.
In Figs. 14 and 15, the dynamic response of the proposed structure to the output frequency change is demonstrated.In Fig. 14, the output frequency has been changed from 50 to 25 Hz, and in Fig. 15, the output frequency has been changed from 50 o 100 Hz.According to these two figures, the proposed structure can feed the output load at different frequencies, and the conditions of dynamic frequency change as well.
Figure 16 displays the voltage and current waveform of the input power supply.The DC value of the input voltage is equal to 23 V, and the peak input current is less than 10 A. Employing soft charging results in drawing suitable limited currents from the input source to charge the capacitors.According to Fig. 16, there is no problem of inrush current to charge the capacitors in the proposed structure.Figure 20 displays the voltage across the switches and power diodes.Figure 20a is related to the voltage stress of power switches S 5 , T 1 , Q 3 , and diode D 1 .According to this figure, the voltage stress of the mentioned power switches is 25%, 50%, and 50% of the peak output voltage, respectively, and the voltage of diode D 1 is 12.5% of the peak output voltage.Figure 20b presents the voltage waveform of power switches S 1 , S 3 , S 4 .According to this figure, the voltage stress of the mentioned switches is 12.5%, 25%, and 25% of the peak output voltage, respectively.Figure 20c also illustrates the voltage stress of power switches Q 1 and Q 4 , which are 50% of the output voltage.Following the results of these figures, the maximum voltage stress of the power switches is half of the output voltage in the proposed structure, which is considered a significant advantage for this structure.The nominal voltage of these switches can be selected as half of the nominal voltage of the inverter, reducing the cost of power electronic devices in the proposed structure.

Conclusion
In this paper, a 17-level single-source structure with octuple voltage gain is proposed.Because the H-bridge module is not utilized in this structure, none of the switches must withstand the maximum output voltage.The maximum blocked voltage of some switches is 50% of the output voltage, and the rest of the switches are less than this value, which makes it possible to employ switches with a nominal voltage lower than the output voltage.To control the charging current of the capacitors, a current limiting inductor is used in the input source path, and the charging current of the capacitors is well limited.Based on the comparison conducted, the proposed structure has the lowest cost factor among compared structures, with a value of 2.04.The THD of the output voltage is 4.98%.The efficiency of the proposed structure in the output power of 1500 W is more than 95%.

Figure 2 .
Figure 2. Current flow paths to generate different voltage levels in the positive half-cycle.

Figure 3 .
Figure 3.The method of discharging capacitors at different voltage levels.

S 1 SFigure 5 .
Figure 5. Losses of the proposed inverter, (a) switching and conduction losses of the switches, (b) conduction losses of the diodes, inductor, and ripple losses of the capacitors.

Figure 8 .
Figure 8. Implementation schematic of the proposed structure.

Figure 9 .
Figure 9. Output voltage and current waveform under resistive-inductive load, (a) simulation, (b) laboratory, (c) THD of the output voltage.

Figure 20 .
Figure 20.The voltage waveform of the two ends of the switches; (a) the voltage between the ends of the switches S 5 , T 1 , Q 3 , and diode D 1 (b) the voltage between the ends of the switches S 1 , S 3 , S 4 , and (c) the voltage between the ends of the switches Q 1 , and Q 4 .

Table 1 .
Switching modes of the proposed structure.

Table 4 .
Comparing the proposed structure with other 17-level switched-capacitor structures.that of the comparative structures.All the comparative structures in this section are of the 17-level single-source switched-capacitor inverter type presented recently.